Arteris Expands Multi-Die Portfolio for AI and HPC Applications

CAMPBELL, Calif., Sept. 15, 2026 /CourierPR/ -- Arteris, a leading provider of semiconductor technology, has expanded its multi-die portfolio to help semiconductor companies transition to chiplet-based architectures. This move is crucial as the industry shifts towards multi-die designs to address the demands of AI computing, particularly in AI, high-performance computing (HPC), and consumer electronics applications.

The new FlexGen Multi-Die product from Arteris addresses a significant challenge in multi-die architectures: the need to maintain performance, efficiency, and predictable traffic behavior when data moves across physical chip boundaries. Previously, data communication within a single system-on-chip (SoC) was straightforward, but transitioning to a multi-die setup requires a new approach to ensure seamless data movement.

Arteris extends network-on-chip (NoC) connectivity transparently across die-to-die links, allowing multiple dies to operate as a unified architecture. This approach supports bidirectional transactions over a single UCIe PHY, reducing the area, power, and I/O requirements by up to 50%. The FlexGen Multi-Die product is specifically designed for non-coherent AI and HPC architectures, providing advanced quality-of-service (QoS) mechanisms to maintain throughput for high-priority traffic across shared die-to-die links.

The expanded portfolio includes Ncore Multi-Die for cache-coherent systems, Magillem integration automation, and Cycuity hardware security assurance. Together, these technologies provide semiconductor engineering teams with a comprehensive solution for increasingly complex multi-die designs, spanning data movement, system integration, and security.

According to K. Charles Janac, president and CEO of Arteris, "Multi-die architectures represent one of the most important changes in semiconductor design since the introduction of the SoC itself. As systems expand beyond the boundaries of a single piece of silicon, the challenge is no longer simply connecting chiplets; it is preserving the intelligence of the architecture across them. Our goal is to help engineering teams gain the benefits of multi-die architectures without having to reinvent the system every time they divide it across another piece of silicon."

Arteris' technology is already being used by its customers as they transition existing architectures from single-die implementations to multi-die products. For instance, Jason Miller, senior director of Silicon Design at AMD, highlighted the importance of solutions that simplify system integration while preserving bandwidth and performance across chiplets.

The broader Arteris multi-die portfolio is designed to support the flexibility and productivity required for next-generation data center, client, gaming, and embedded compute products. As multi-die adoption expands, interoperability among NoC technologies, die-to-die interfaces, chiplet IP, design tools, and advanced packaging technologies will become increasingly important. Arteris is working with semiconductor IP and ecosystem partners to help reduce integration risk and establish more reusable foundations for multi-die design.

Arteris' expansion of its multi-die portfolio underscores the company's commitment to supporting the industry's transition to chiplet-based architectures. By providing transparent data movement solutions, Arteris is helping engineering teams improve design reuse, reduce integration complexity, and bring differentiated products to market faster.