Alchip, Synopsys Collaborate on Data Center Bandwidth Solution

SAN JOSE, Calif., Sept. 23, 2026 /CourierPR/ -- Today at the TSMC 2026 North America Open Innovation Platform® (OIP) Ecosystem Forum, Alchip Technologies presented a technical paper with Synopsys on how AI data center ASICs can overcome increasingly stringent bandwidth requirements as scale-up and out interfaces become critical to next-generation system architectures. This approach brings together Synopsys 224G PHY IP with Alchip’s advanced packaging and signal integrity/power integrity (SI/PI) expertise in a protocol-agnostic physical design.

The collaboration addressed several key physical design challenges, including die-edge congestion and escape routing complexity, along with signal and power integrity constraints across both die and package. Limited die-edge real estate and asymmetric constraints between East/West (E/W) and North/South (N/S) edges were also considered, along with dense package substrate breakout requirements that must be met without degrading channel performance.

The presentation highlighted how the coordinated optimization of escape routing, die-edge utilization, and package breakout could balance signal and power integrity requirements to maintain overall system performance. Differentiated handling of E/W and N/S die edges further ensured that maximum bandwidth per millimeter of die-edge beachfront was achieved at max reach, consistently across all die edges.

Building on this work, the analysis extended to E/W package breakout techniques needed to sustain 1.6 terabits per second (Tbps) of networking bandwidth, highlighting key routing considerations and SI/PI considerations at the substrate level. The resulting protocol-agnostic, forward-scalable physical design approach provides a foundation that can ultimately support 448G SerDes implementations.

Using this collaborative methodology, engineers achieved chip-to-chip interconnect bandwidth approaching theoretical physical limits, demonstrating the feasibility of ultra-high-density 224G scale-up interconnect implementations within realistic die edge and package constraints. These results point to broader implications for data center design, as AI accelerators and high-performance networking ASICs continue to scale, maximizing bandwidth per millimeter directly impacts system throughput and scalability.

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global High-Performance Computing and AI infrastructure ASIC provider of IC and packaging design, and production services for companies developing complex and high-volume ASICs and SoCs. The company has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D CoWoS packaging, chiplet design, and manufacturing management. Customers include global leaders in artificial intelligence, high-performance computing, supercomputing, mobile communications, entertainment devices, networking equipment, and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).